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Eastern Mediterranean University

Digital Logic Systems (BLGM224)

Synchronous Sequential Logic; Latches, Circuit Delay Model, Flip-Flops. Mealy and Moore Models for Sequential Circuits. Analysis of Clocked Sequential Circuits. Introduction to Sequential Circuit Design. State Reduction and Assignment. Flip-Flop Excitation Tables. Design Procedure. Design of Counters. Registers, Counters and the Memory Unit; Registers, Shift Registers. Ripple Counters. Synchronous Counters, Timing Sequences. Random Access Memory (RAM), Memory Decoding. Implementation Technology; Programmable Logic Devices (ROM, PLA, PAL, CPLD, FPGA). Algorithmic State Machines (ASM); ASM Flow Chart. Timing Considerations. Control Implementation. Asynchronous Sequential Circuits; Flow Table. Transition Table. Race Condition. Implementation with Lumped Delay Elements and Latches. Glitches and Hazards. (Pre-requisite: CMPE 223)

Credit: 4

Lecture Hour (hrs/week): 4

Lab (hrs/week): 0

Tutorial (hrs/week): 1

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